Assessments - 2, GPA: 3
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• Disable the L1 cache. • Set up a channel of the 8254 Timer chip to count for a predetermined amount of time. • Read the CPU RTSC and save the initial count value. • Poll counter and wait for it to roll over. • Read the CPU RTSC and save as the final count. • Subtract the initial value of the RTSC from the final value. • EDX:EAX now contains the number of clock ticks in the predetermined amount of time. To get the value in MHz, divide the number of clocks by the time represented in microseconds (i.e., 5 ms = 5000). 4.1.2.1 CPU Identification The CPUID check should be done as soon as possible. Use the CPUID instruction. Check the Major and Minor Revision fields located in the GLCP_CHIP_REVID register (MSR Address 4C000017h[7:0]) for the silicon revision. 4.1.3 Memory Controller Initialization Registers: MC_CF07_DATA (MSR Address 2000018h) MC_CF8F_DATA (MSR Address 2000019h) MC_CFCLK_DBUG (MSR Address 200001Dh) The memory controller in the GX processor supports SDRAM and DDR memory. The memory controller and the RAM are programmed via settings read from the SPD. The SPD is required for detection of PC66, PC100, PC133 and DDR RAM. In the case of a closed system, where the RAM is soldered to the motherboard and there is no SPD, memory settings can be stored in CMOS for initialization. The SDRAM clock is set up prior to reset by the clock initialization. • Address, bank, registered/unbuffered, and other values read from the SPD. • Size memory in DIMM socket(s). • Program Memory Controller. • Set default refresh to an appropriate value. AMD Geode™ GX Processor/CS5535 Companion Device GeodeROM Porting Guide Initialization 32430C 4.1.3.1 Size Memory Entry Conditions: 4 GB descriptor in FS Core register. Procedure: For each DIMM: • Set the following in the MC_CF07_DATA register MSR Address 20000018h): — Module Banks per DIMM – SPD byte 5: Number of DIMM Banks — Banks per SDRAM device – SPD byte 17: Number of Banks on SDRAM device — DIMM size - Size = Density * Banks – SPD byte 5: Number of DIMM Banks – SPD byte 31: Module Bank Density — Page size - Page size = 2^# Column Addresses – SPD byte 4: Number of Column Addresses • Set CAS Latency in MC_CF8F_DATA register (MSR Address 20000019h): — SPD byte 18: CAS Latency — Turn on the memory interface in MC_CFCLK_DBUG bit MASK_CKE[1:0] (MSR Address 2000001Dh[9:8]). — Do 12 refreshes (CF07_PROG_DRAM) for the Memory Controller to synchronize. — Set the refresh rate of the DIMM – SPD byte 12: Refresh Rate/Type. — Load RDSYNC counter with sync value. Note: See the AMD Geode™ GX Processors Data Book (publication ID 31505) for bit descriptions and allocation. 4.1.4 Test Extended DRAM Entry Conditions: 4 GB descriptor in FS Core register. All memory configured. Procedure: • Set GLIU descriptor to allow writes to memory. • Make sure interface is turned on in MC_CFCLK_DBUG bit MASK_CKE[1:0] (MSR Address 2000001Dh[9:8]). • Determine total amount of memory by doing a read/write test. • For each 1 MB block of memory: 1) Walk a 1 through data bus at first location of block. 2) Walk a 0 through data bus at first location of block. 3) Check for stuck address line in the block. • Continue test if no memory present for debug purposes. 4.1.5 GeodeLink™ Modules Initialization Descriptors routing memory and I/O for GX processor modules are initialized by GeodeROM and Virtual System Architecture ™ (VSA) technology. GeodeLink modules that are virtualized by VSA technology and use PCI memory or PCI I/O, report that resource in the virtual PCI header. The GLIU is configured with MSRs like all GX processor modules. AMD Geode™ GX Processor/CS5535 Companion Device GeodeROM Porting Guide 32430C Initialization 4.1.5.1 GLIU Descriptors Initialization Register: P2D_BM, P2D_BMO, P2D_R, P2D_RO, P2D_SC (GLIU0 MSR Address 10000020h-1000003Fh, GLIU1 MSR Address 40000020h-1000003Fh) IO_BM, IO_SC (GLIU0 MSR Address 100000E0h-100000FFh, GLIU1 MSR Address 400000E0h-400000FFh) Set up system memory map with GeodeLink Descriptors and Region Control Registers (RConfs). Descriptors and RConfs must match each other. These register maps will look like the memory map from INT 15h AX = E820. The responsibility of setting Descriptors and RConfs is split between GeodeROM and VSA technology. GeodeROM handles settings for system memory and VSA memory. Then the responsibility is handed off to VSA technology once it is loaded to handle all other memory and I/O routing. This is most notable in the frame buffer initialization. See Memory Map, Figure 7-2 on page 31 for a pictorial representation. 4.1.5.2 GLIU Priority Initialization Each GeodeLink module has standard MSRs. GLD_MSR_CONFIG is one of the standard registers located at address 2001h in the GX processor and 0001h in the CS5535 companion device. Two fields in some of the GLD_MSR_CONFIG registers can affect the module priority: Priority Level (PRI0) and Priority Domain (PID). These values default to zero. In the case of data starvation or saturation on the GLIU, GeodeRO...