Assessments - 1, GPA: 4
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not included) 54(W) x 132(H) x 35(D) mm; 25/32(W) x 5316(H) x 138(D) inch Weight (with BP-209) 355 g; 12.5 oz TRANSMITTER Output power High 4 W Low 1 W Modulation system Variable reactance frequency modulation Max. freqequency deviation ±5.0 kHz (W-type), ±4.0 kHz (M-type)*3, ±2.5 kHz (N-type) Spurious emissions 0.25 pW @ < 1 GHz, 1.0 pW @ < 1 GHz 73 dBc typical Adjacent channel power 70 dB (W/M-type) 60 dB (N-type) 70 dB typical (25 kHz) 60 dB typical (12.5 kHz) Transmitter audio distortion Less than 5% at 1 kHz, 60% deviation Less than 3% at 1 kHz, 40% deviation Limitting charact of modulator 70-100% of max. deviation Ext. microphone connector 3-conductor 2.5(d) mm (1/10")/2.2 kQ RECEIVER Receive system Double-conversion superheterodyne system Intermediate frequencies 1st: 46.350 MHz, 2nd: 450 kHz Sensitivity (typical) 0.3 pV at 12 dB SINAD 0.79 pV (emf) at 20 dB SINAD 0.3 pV at 12 dB SINAD Squelch sencitivity 0.3 pV typical (at threshold) Adjacent channel selectivity 70 dB (W/M-type) 60 dB (N-type) 75 dB typical (W-type) 65 dB typical (N-type) Spurious response 70 dB 70 dB typical Intermoduration rejection ratio 65 dB 70 dB typical Hum and noise 45 dB typical (W/M-type) 43 dB typical (N-type) 45 dB typical (25 kHz) 40 dB typical (12.5 kHz) Audio output power (at 7.2 V DC) 500 mW typical at 5% distortion with an 8 Q load External SP connector 3-conductor 3.5(d) mm (V8")/8 Q Measurements made in accordance with EIA/TIA-152-C, 204-D, 603 or ETS 300-086. *1EIA/TIA version only, *2General version only, *3ETS/CEPT version only All stated specifications are subject to change without notice or obligation. 1 - 1 SECTION 2 INSIDE VIEWS • MAIN UNIT TOP VIEW BOTTOM VIEW Antenna switcing circuit (D2, D8: MA77) Power amplifier- (Q1: 2SK2974) APC - IC3A: NJM3403AV\ Q37: DTA144EU IF amplifier- (Q14: 2SC4215 O) PLL IC - (IC1: |iPD3140GS) TX/RX switch — (D3, D4: MA77) Mic amplifier circuit Antenna switcing circuit (D1: 1SV307) 1st mixer (Q13: 3SK239A) VCO circuit D/A converter (IC10: M62363FP-650C) EEPROM 1IC7: HN58X2432TI [OTHER] HN58X2464TI [100 channel version] CPU (IC8: HD6433876B50H) Low pass filter circuit 2 - 1 SECTION 3 DISASSEMBLY AND OPTION INSTRUCTIONS 3-1 DISASSEMBLY INSTRUCTION • REMOVING THE CHASSIS PANEL © Unscrew 1 nut @, and remove 1 knob ®. © Unscrew 2 screws ©. @ Take off the chassis in the direction of the arrow. © Unplug J6 to separate front panel and chassis. • REMOVING THE MAIN UNIT © Remove the searing rubber. © Unsolder 4 points ®, and unscrew 1 nut ©. © Unscrew 3 screws ©, and 6 screws © (silver, 2 mm) to separate the chassis and the MAIN unit. © Take off the MAIN unit in the direction of the arrow. 3 - 1 3-2 OPTIONAL UNIT INSTALLATIONS © Remove the option cover. © Connect one of UT-96, UT-105, UT-108, UT-109, UT-110, UT-111, and UT-113 optional units to J5. @ Replace the option cover to the chassis-hole. 3 - 2 SECTION 4 CIRCUIT DESCRIPTION 4-1 RECEIVER CIRCUITS 4-1-1 ANTENNA SWITCHING CIRCUIT The antenna switching circuit functions as a low-pass filter while receiving. However, its impedance becomes very high while D2 and D8 are turned ON. Thus transmit signals are blocked from entering the receiver circuits. The antenna switching circuit employs a ty4 type diode switching system. Received signals are passed through the low-pass filter (L1, L2, C3, C8, C666). The filtered signals are applied to the V4 type antenna switching circuit (D2, D8). The passed signals are then applied to the RF amplifier circuit. 4-1-2 RF CIRCUIT The RF circuit amplifies signals within the range of frequency coverage and filters out-of-band signals. The signals from the antenna switching circuit are amplified at the RF amplifier (Q12) after passing through the tunable bandpass filter (L17, D10, C85, C86). The amplified signals are applied to the 1st mixer circuit (Q13) after out-of-band signals are suppressed at the 3 stages tunable bandpass filter (D401, L18, C89, C406, D11, L402, C91, C92, C94, D12, L19, C97, C98). Varactor diodes are employed at the bandpass filters that track the filters and are controlled by the CPU (IC8) via the expander IC (IC10) using T1-T4 signals. These diodes tune the center frequency of an RF passband for wide bandwidth receiving and good image response rejection. The signals from the RF circuit are mixed at the 1st mixer (Q13) with a 1st LO signal coming from the VCO circuit to produce a 46.35 MHz 1st IF signal. The 1st IF signal is applied to a pair of crystal filters (FI1) to suppress out-of-band signals. The filtered 1st IF signal is applied to the IF amplifier (Q14), then applied to the 2nd mixer circuit (IC2, pin 16). 4-1-4 2ND IF AND DEMODULATOR CIRCUITS The 2nd mixer circuit converts the 1st IF signal into a 2nd IF signal. A double conversion superheterodyne system (which converts receive signals twice) improves the image rejection ratio and ...
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