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Instruções de Operação Gigabyte, Modelo GA-EX58-UD5

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END The power supply, CPU or CPU socket might fail. The keyboard or mouse might fail. A Turn off the computer and connect the IDE/SATA devices. Check if the system can boot successfully. Press to enter BIOS Setup. Select "Load Fail-Safe Defaults" (or "Load Optimized Defaults"). Select "Save & Exit Setup" to save changes and exit BIOS Setup. The problem is verified and solved. The problem is verified and solved. The problem is verified and solved. The problem is verified and solved. T h e I D E / S A T A device, connector, or cable might fail. GA-EX58-UD5P/UD5 Motherboard - 118 - POST (hex) Description CFh Test CMOS R/W functionality C0h Early chipset initialization: - Disable shadow RAM - Program basic chipset registers C1h Detect memory - Auto-detection of DRAM size, type and ECC C3h Expand compressed BIOS code to DRAM C5h Call chipset hook to copy BIOS back to E000 & F000 shadow RAM 01h Expand the Xgroup codes locating in physical address 1000:0 02h DualBIOS init (optional) 03h Initial Superio_Early_Init switch 05h 1. Blank out screen 2. Clear CMOS error flag 07h 1. Clear 8042 interface 2. Initialize 8042 self-test 08h 1. Test special keyboard controller for Winbond 977 series Super I/O chips 2. Enable keyboard interface 0Ah 1. Disable PS/2 mouse interface (optional) 2. Auto detect ports for keyboard & mouse followed by a port & interface swap (optional) 3. Reset keyboard Super I/O chips 0Eh Test F000h segment shadow to see whether it is R/W-able or not. If test fails, keep beeping the speaker 10h Auto detect flash type to load appropriate flash R/W codes into the run time area in F000 for ESCD & DMI support 12h Use walking 1's algorithm to check out interface in CMOS circuitry. Also set real-time clock power status, and then check for override 14h Program chipset default values into chipset. Chipset default values are MODBINable by OEM customers 16h Initial onboard clock generator if Early_Init_Onboard_Generator is defined See also POST 26h 18h Detect CPU information including brand, SMI type and CPU level 1Bh Initial interrupts vector table. If no special specified, all H/W interrupts are directed to SPURIOUS_INT_HDLR & S/W interrupts to SPURIOUS_soft_HDLR 1Dh Initial EARLY_PM_INIT switch 23h 1. Check validity of RTC value: e.g. a value of 5Ah is an invalid value for RTC minute 2. Load CMOS settings into BIOS stack. If CMOS checksum fails, use default value instead 5-4 POST Error Code - 119 - Appendix POST (hex) Description 24h Prepare BIOS resource map for PCI & PnP use. If ESCD is valid, take into consideration of the ESCD's legacy information 25h Early PCI initialization: - Enumerate PCI bus number - Assign memory & I/O resource - Search for a valid VGA device & VGA BIOS, and put it into C000:0 26h 1. If Early_Init_Onboard_Generator is not defined Onboard clock generator initialization. Disable respective clock resource to empty PCI & DIMM slots 2. Init onboard PWM 3. Init onboard H/W monitor devices 27h Initialize INT 09 buffer 29h 1. Program CPU internal MTRR for 0-640K memory address 2. Initialize the APIC for Pentium class CPU 3. Program early chipset according to CMOS setup Example: onboard IDE controller 4. Measure CPU speed 2Bh Invoke video BIOS 2Dh 1. Initialize double-byte language font (optional) 2. Put information on screen display, including Award title, CPU type, CPU speed, full screen logo 33h Reset keyboard if Early_Reset_KB is defined e.g. Winbond 977 series Super I/O chips. See also POST 63h 35h Test DMA Channel 0 37h Test DMA Channel 1 39h Test DMA page registers 3Ch Test 8254 3Eh Test 8259 interrupt mask bits for channel 1 40h Test 8259 interrupt mask bits for channel 2 43h Test 8259 functionality 47h Initialize EISA slot 49h 1. Calculate total memory by testing the last double word of each 64K page 2. Program write allocation 4Eh 1. Program MTRR of M1 CPU 2. Initialize L2 cache for P6 class CPU & program CPU with proper cacheable range 3. Initialize the APIC for P6 class CPU 4. On MP platform, adjust the cacheable range to smaller one in case the cacheable ranges between each CPU are not identical 50h Initialize USB Keyboard & Mouse 52h Test all memory (clear all extended memory to 0) 53h Clear password according to H/W jumper (optional) 55h Display number of processors (multi-processor platform) GA-EX58-UD5P/UD5 Motherboard - 120 - POST (hex) Description 57h 1. Display PnP logo 2. Early ISA PnP initialization - Assign CSN to every ISA PnP device 59h Initialize the combined Trend Anti-Virus code 5Dh 1. Initialize Init_Onboard_Super_IO 2. Initialize Init_Onbaord_AUDIO 60h Okay to enter Setup utility; i.e. not until this POST stage can users enter the CMOS setup utility 63h Reset keyboard is Early_Reset_KB is not defined 65h Initialize PS/2 Mouse 67h Prepare memory size information for function call: INT 15h ax=E820h 69h Turn on L2 cache 6Bh Program chipset registers according to items described in Setup & Auto-configuration table 6Dh 1. Assign resources to all ISA PnP devi...


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