Assessments - 3, GPA: 4.7
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The output of the mixer core is taken directly from its open collectors. The open collector outputs present a high impedance at the IF frequency. The conversion gain of the mixer depends directly on the impedance presented to these open collectors. In characterization, a 100 . load was presented to the part via a 2:1 impedance transformer. The device also features a power-down function. Application of a logic low at the PWDN pin allows normal operation. A high logic level at the PWDN pin shuts down the AD8342. Power consumption when the part is disabled is less than 10 mW. The bias for the mixer is set with an external resistor (RBIAS) from the EXRB pin to ground. The value of this resistor directly affects the dynamic range of the mixer. The external resistor should not be lower than 1.82 k.. Permanent damage to the part could result if values below 1.8 k. are used. This resistor sets the dc current through the mixer core. The performance effects of changing this resistor can be seen in the Typical Per- formance Characteristics section. Adobe Systems 05352-040LOINPUTVPLOIFOPIFOMRFINRFCMBIASEXTERNALBIASRESISTORVPDCPWDNVTOI Figure 39. Simplified Schematic Showing the Key Elements of the AD8342 As shown in Figure 40, the IF output pins, IFOP and IFOM, are directly connected to the open collectors of the NPN transistors in the mixer core so the differential and single-ended imped- ances looking into this port are relatively high—on the order of several k.. A connection between the supply voltage and these output pins is required for proper mixer core operation. Adobe Systems 05352-041IFOPIFOMLOINRFCMRFINCOMM Figure 40. AD8342 Simplified Schematic The AD8342 has three pins for the supply voltage: VPDC, VPMX, and VPLO. These pins are separated to minimize or eliminate possible parasitic coupling paths within the AD8342 that could cause spurious signals or reduced interport isolation. Consequently, each of these pins should be well bypassed and decoupled as close to the AD8342 as possible. AC INTERFACES The AD8342 is designed to downconvert radio frequencies (RF) to lower intermediate frequencies (IF) using a high or low-side local oscillator (LO). The LO is injected into the mixer core at a frequency higher or lower than the desired input RF. The difference between the LO and the RF , fLO . fRF, (high side) or fRF . fLO (low side) is the intermediate frequency, fIF. In addition to the desired RF signal, an RF image is downconverted to the desired IF frequency. The image frequency is at fLO + fIF when driven with a high side LO . When using a broadband load, the conversion gain of the AD8342 is nearly constant over the specified RF input band (see Figure 3). The AD8342 is designed to operate over a broad frequency range. It is essential to ac-couple RF and LO ports to prevent dc offsets from skewing the mixer core in an asymmetrical man- ner, potentially degrading noise figure and linearity. The RF input of the AD8342 is high impedance, 1 k. across the frequency range shown in Figure 41. The input capacitance decreases with frequency due to package parasitics. Adobe Systems 2.001.000001G05352-042FREQUENCY (Hz) RESISTANCE (k.) CAPACITANCE (pF) 1.751.500.751.251.000.500.750.500.250.25100M200M300M400M500M600M700M800M900M Figure 41. RF Input Impedance The matching or termination used at the RF input of the AD8342 has a direct effect on its dynamic range. The charac- terization circuit, as well as the evaluation board, uses a 100 . resistor to terminate the RF port. This termination resistor in shunt with the input stage results in a return loss of better than .10 dBm (relative to 50 .). Table 4 shows gain, IP3, P1dB, and noise figure for four different input networks. This data was measured at an RF frequency of 250 MHz and at an LO frequency of 300 MHz. Table 4. Dynamic Performance for Various Input Networks Input Network 50 . Shunt 100 . Shunt 500 . Shunt Matched (Fig. 40) Gain (dB) 0.66 3.5 5.3 9.3 IIP3 (dBm) 25.4 22.9 20. 6 18.5 P1dB (dBm) 10.8 8.4 6.3 2.3 NF (dB) 14 12.5 10.2 10.5 The RF port can also be matched using an LC circuit, as shown in Figure 42. Adobe Systems 05352-043ZL1k.ZO = 50.fMAIN = 250MHz 50.3.6pF100nH(1000 + j0). Figure 42. Matching Circuit Impedance transformations of greater than 10:1 result in a higher Q circuit and thus a narrow RF input bandwidth. A 1 k. resistor is placed across the RF input of the device in parallel with the device internal input impedance, creating a 500 . load. This impedance is matched to as close as possible to 50 . for the source, with standard components using a shunt C, series L matching circuit (see Figure 43). Adobe Systems 05352-04425.010.010.025.050.0100.0200.0500.0500.0200.0100.050.0Q = 3.01234 Point 1(1000.0 + j0.0). Q = 0.0 at 250.000 MHz Point 2(500.0 + j0.0). Q = 0.0 at 250.000 MHz Point 3(55.6 . j157.2). Q = 2.8 at 250.000 MHz Point 4(55.6 . j0.1). Q = 0.0 at 250.000 MHz Figure 43. LC Matching Example IF PORT The IF port comprises open-collector differen...
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