Assessments - 2, GPA: 3
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The CY7C1353G is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133-MHz device). Write operations are controlled by the two Byte Write Select (BW[A:B]) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. To avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. C MODE BWA BWB WE CE1 CE2 CE3 OE READ LOGIC DQs DQPA DQPB MEMORY ARRAY EINPUT REGISTER ADDRESS REGISTER WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BURST LOGIC A0' A1'D1 D0 Q1 Q0A0 A1 ADV/LD CE ADV/LD C CLK CEN WRITE DRIVERS D A T A S T E E R I N G S E N S E A M P S WRITE ADDRESS REGISTER A0, A1, A O U T P U T B U F F E R S E ZZ SLEEP CONTROL Logic Block Diagram Note: 1.For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document #: 38-05515 Rev. *E Revised July 09, 2007 [+] Feedback CY7C1353G Selection Guide 133 MHz 100 MHz Unit Maximum Access Time 6.5 8.0 ns Maximum Operating Current 225 205 mA Maximum CMOS Standby Current 40 40 mA Pin Configuration 100-Pin TQFP Pinout AAAAA1A0NC/288MNC/ 144MV SS V DDNC/36MAAAAAA NC NC NC VDDQ VSS NC NC DQB DQB VSS VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC AACE1 CE2NCNCBWB BWA CE3 V DD V SSCLKWECENOENC/18MAA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 3132333435363738394041424344454647484950 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 10099989796959493929190898887868584838281 A NC/9MADV/ LD MODENC/72M CY7C1353G BYTE B A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC BYTE A Document #: 38-05515 Rev. *E Page 2 of 13 [+] Feedback CY7C1353G Pin Definitions Name IO Description A0, A1, A Input- Synchronous Address Inputs used to select one of the 256K address locations. Sampled at the rising edge of the CLK. A[1:0] are fed to the two-bit burst counter. BW[A:B] Input- Synchronous Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. WE Input- Synchronous Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. ADV/LD Input- Synchronous Advance/Load Input. Used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD must be driven LOW to load a new address. CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. CE1 Input- Synchronous Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2, and CE3 to select/deselect the device. CE2 Input- Synchronous Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. CE3 Input- Synchronous Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. OE Input- Asynchronous Output Enable, asynchronous input, Active LOW. Combined with the synchronous logic block inside the device to control the direction of the IO pins. When LOW, the IO pins are allowed to behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, when the device has been deselected. CEN Input- Synchronous Clock Enable Input, Active LOW. When asserted LOW the Clock signal is recognized by the SRAM. When deasserted HIGH the Clock signal is masked. While deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. ZZ Input- Asynchronous ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity prese...