Assessments - 3, GPA: 3.7
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A 64/65 or a 128/129 for the 4000 MHz prescaler, and a 32/33 or a 64/65 for the 2000 MHz prescaler can be selected for the prescaler that enables pulse swallow operation. The BiCMOS process is used, as a result a supply current is typically 9.0 mA at 3.0 V. The supply voltage range is from 2.7 V to 3.6 V. A refined charge pump supplies well-balanced output current with 1.5 mA and 6 mA selectable by serial date. The pin assignments are the same as MB15F78UL. Fast locking is achieved for adopting the new circuit. The new package (BCC20) decreases a mount area of MB15F74UL more than 30% comparing with the former BCC16 (for dual PLL) . ■ FEATURES • High frequency operation : RF synthesizer : 4000 MHz Max : IF synthesizer : 2000 MHz Max • Low power supply voltage : Vcc = 2.7 to 3.6 V • Ultra low power supply current : Icc = 9.0 mA Typ (Vcc = Vp = 3.0 V, Ta = +25 °C, SWif = SWrf = 0 in IF/RF locking state) (Continued) ■ PACKAGE FUJITSU MB15F74UL (Continued) • Direct power saving function : Power supply current in power saving mode Typ 0.1 |jA (Vcc = Vp = 3.0 V, Ta = +25 ° C) Max 10 |JA (Vcc = Vp = 3.0 V) • Software selectable charge pump current : 1.5 mA/6.0 mA Typ • Dual modulus prescaler : 4000 MHz prescaler (64/65 or128/129) /2000 MHz prescaler (32/33 or 64/65) • 23 bit shift register • Serial input binary 14-bit programmable reference divider : R = 3 to 16,383 • Serial input programmable divider consisting of: - Binary 7-bit swallow counter : 0 to 127 - Binary 11-bit programmable counter : 3 to 2,047 • Built-in high-speed tuning, low-noise phase comparator, current-switching type constant current circuit • On-chip phase control for phase comparator • On-chip phase comparator for fast lock and low noise • Built-in digital locking detector circuit to detect PLL locking and unlocking • Operating temperature : Ta = -40 ° C to +85 ° C ■ PIN ASSIGNMENTS (BCC-20) TOP VIEW finiF XfiniF GNDif VCCIF PSiF VpiF OSCin Data GND Clock 1 ¡20 ¡19 ¡¡18 ¡17 16 [2_~. [3_". [4_". 15.: 14.: J_3“J 12 ¡6 17 ::8 ::9 :no: L _ 11___11__IL _ 1 11 Doif Dorf LD/fout VpRF LE finRF XfinRF GNDrf Vccrf PSrf (LCC-20P-M05) 2 MB15F74UL ■ PIN DESCRIPTION Pin no. Pin name I/O Descriptions 1 finiF I Prescaler input pin for the IF-PLL. Connection to an external VCO should be AC coupling. 2 XfiniF I Prescaler complimentary input for the IF-PLL section. This pin should be grounded via a capacitor. 3 GNDif — Ground pin for the IF-PLL section. 4 Vccif — Power supply voltage input pin for the IF-PLL section (except for the charge pump circuit) , the shift register and the oscillator input buffer. 5 PSif I Power saving mode control pin for the IF-PLL section. This pin must be set at “L” when the power supply is started up. (Open is prohibited.) PSif = “H”; Normal mode/PSIF = “L” ; Power saving mode 6 V i F — Power supply voltage input pin for the IF-PLL charge pump. 7 Doif O Charge pump output for the IF-PLL section. 8 LD/fout O Lock detect signal output (LD) /phase comparator monitoring output (fout) pin. The output signal is selected by LDS bit in a serial data. LDS bit = “H” ; outputs fout signal/LDS bit = “L” ; outputs LD signal 9 Dorf O Charge pump output for the RF-PLL section. 10 F R Œ V — Power supply voltage input pin for the RF-PLL charge pump. 11 F R S P I Power saving mode control for the RF-PLL section. This pin must be set at “L” when the power supply is started up. (Open is prohibited. ) PSrf = “H” ; Normal mode/PSRF = “L” ; Power saving mode 12 VCCRF — Power supply voltage input pin for the RF-PLL section (except for the charge pump circuit) 13 GNDRF — Ground pin for the RF-PLL section 14 XfinRF I Prescaler complimentary input pin for the RF-PLL section. This pin should be grounded via a capacitor. 15 finRF I Prescaler input pin for the RF-PLL. Connection to an external VCO should be via AC coupling. 16 LE I Load enable signal input pin (with the schmitt trigger circuit) When LE is set “H”, data in the shift register is transferred to the corresponding latch according to the control bit in a serial data. 17 Data I Serial data input pin (with the schmitt trigger circuit) Data is transferred to the corresponding latch (IF-ref. counter, IF-prog. counter, RF-ref. counter, RF-prog. counter) according to the control bit in a serial data. 18 Clock I Clock input pin for the 23-bit shift register (with the schmitt trigger circuit) One bit data is shifted into the shift register on a rising edge of the clock. 19 OSCin I The programmable reference divider input pin. TCXO should be connected with an AC coupling capacitor. 20 GND — Ground pin for OSC input buffer and the shift register circuit. 3 MB15F74UL ■ BLOCK DIAGRAM 4 MB15F74UL ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Min Max Power supply voltage Vcc - 0.5 4.0 V Vp Vcc 4.0 v Input voltage Vi - 0.5 Vcc + 0.5 v Output voltage LD/fout Vo GND Vcc v Doif, Dorf Vdo GND Vp v Storage temperatu...