Assessments - 4, GPA: 4
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• Binary 11-bit Programmable Counter Data Setting Divide ratio N11 N10 N9N8N7N6N5N4N3N2N1 3 0 0 0 0 0 0 0 0 0 1 1 4 · · · 2047 0 · · · 1 0 · · · 1 0 · · · 1 0 · · · 1 0 · · · 1 0 · · · 1 0 · · · 1 0 · · · 1 1 · · · 1 0 · · · 1 0 · · · 1 Note : Divide ratio less than 3 is prohibited • Binary 7-bit Swallow Counter Data Setting Divide ratio A7 A6 A5 A4 A3 A2 A1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 · · · · · · · · · · · · · · · · · · · · · · · · 127 1 1 1 1 1 1 1 MB15F74UV • Prescaler Data Setting Divide ratio SW = ==== “1” SW = ==== “0” Prescaler divide ratio IF-PLL 32/33 64/65 Prescaler divide ratio RF-PLL 64/65 128/129 • Charge Pump Current Setting Current value CS ± 6.0 mA 1 ± 1.5 mA 0 • LD/fout output Selectable Bit Setting LD/fout pin state LDS T1 T2 0 0 0 LD output 0 1 0 0 1 1 fout output frIF 1 0 0 frRF 1 1 0 fpIF 1 0 1 fpRF 1 1 1 • Phase Comparator Phase Switching Data Setting Phase comparator input FCIF, RF = ==== “1” FCIF, RF = ==== “0” DoIF, DoRF DoIF, DoRF fr > fp H L fr < fp L H fr = fp Z Z Z : High-impedance Depending upon the VCO and LPF polarity, FC bit should be set. High (1) VCO polarity FC = “1” (2) VCO polarity FC = “0” VCO Output Frequency (1) (2) Max LPF Output voltage Note : Give attention to the polarity for using active type LPF. MB15F74UV 3. Power Saving Mode (Intermittent Mode Control Circuit) Status PS pin Normal mode H Power saving mode L The intermittent mode control circuit reduces the PLL power consumption. By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See the Electrical Characteristics chart for the specific value. The phase detector output, Do, becomes high impedance. For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table. Setting the PS pin high, releases the power saving mode, and the device works normally. The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation. When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparaor output, resulting in a VCO frequency jump and an increase in lockup time. To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation. Notes : · When power (VCC) is first applied, the device must be in standby mode. · PS pin must be set “L” at Power-ON. ONOFF VCC Clock Data LE PS (1) (2) (3) tPS . 100 ns tV . 1 m s (1) PS = L (power saving mode) at Power-ON (2) Set serial data at least 1 m s after the power supply becomes stable (VCC . 2.2 V) . (3) Release power saving mode (PSIF, PSRF : “L” ® “H”) at least 100 ns later after setting serial data. MB15F74UV 4. Serial Data Data Input Timing Divide ratio is performed through a serial interface using the Data pin, Clock pin, and LE pin. Setting data is read into the shift register at the rise of the Clock signal, and transferred to a latch at the rise of the LE signal. The following diagram shows the data input timing. LSBMSB Clock Data LE t7 t1 t2 t3 t4 t5 t6 1st data 2nd data Control bit Invalid data Note : LE should be “L” when the data is transferred into the shift register. Parameter Min Typ Max Unit Parameter Min Typ Max Unit t1 20 . . ns t5 100 . . ns t2 20 . . ns t6 20 . . ns t3 30 . . ns t4 30 . . ns t7 100 . . ns MB15F74UV ¦ nnnn PHASE COMPARATOR OUTPUT WAVEFORM • LD Output Logic Notes : · Phase error detection range = - 2p to +2p · Pulses on DoIF/RF signals during locking state are output to prevent dead zone. · LD output becomes low when phase error is tWU or more. · LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more. · tWU and tWL depend on OSCIN input frequency as follows. tWU . 2/fosc : e.g. tWU . 156.3 ns when fosc = 12.8 MHz tWU . 4/fosc : e.g. tWL . 312.5 ns when fosc = 12.8 MHz IF-PLL section RF-PLL section LD output Locking state/Power saving state Locking state/Power saving state H Locking state/Power saving state Unlocking state L Unlocking state Locking state/Power saving state L Unlocking state Unlocking state L frIF/RF fpIF/RF LD DoIF/RF tWU tWL DoIF/RF H L L H Z Z (FC bit = “1”) (FC bit = “0”) MB15F74UV ¦ nnnn TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCIN) LD/ fout DoIF VCCIF 1000 pF 0.1 m F 0.1 m F PSIF GNDIF finIF XfinIF GND OSCIN DoRF VCCRF PSRF GNDRF XfinRF finRF LEDataClock S.G. S.G. S.G. 1000 pF 50 W 1000 pF 50 W 1000 pF 50 W 109876 5 4 3 2 1 11 12 13 14 15161718 MB15F74UV 1000 pF VCCRF VCCIF Oscilloscope Controller (divide ratio setting) MB15F74UV ¦ nnnn TYPICAL CHARACTERISTICS 1. fin input sensitivity 10 1500 2000 2500 3000 3500 4000 4500 5000 VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V SPEC 0 - 10 - 20 - 30 - 40 - 50 PfinRF [dBm] finRF [MHz] Ta = +25 C Catalog guaranteed ra...