Assessments - 5, GPA: 3.6
(
)
)
|
Facilidade de uso
Selectable skew to 18 ns . Inverted and non-inverted . Operation at 1.2 and 1.4 input frequency . Operation at 2x and 4x input frequency (input as low as 3.75 MHz) ¦ Zero input to output delay ¦ 50% duty cycle outputs ¦ Outputs drive 50. terminated lines ¦ Low operating current ¦ 32-pin PLCC/LCC package ¦ Jitter < 200 ps peak-to-peak (< 25 ps RMS) Functional Description The CY7B991 and CY7B992 Programmable Skew Clock Buffers (PSCB) offer user selectable control over system clock functions. These multiple output clock drivers provide the system integrator with functions necessary to optimize the timing of high performance computer systems. Each of the eight individual drivers, arranged in four pairs of user controllable outputs, can drive terminated transmission lines with impedances as low as 50.. They can deliver minimal and specified output skews and full swing logic levels (CY7B991 TTL or CY7B992 CMOS). Each output is hardwired to one of the nine delay or function configurations. Delay increments of 0.7 to 1.5 ns are determined by the operating frequency with outputs that skew up to ±6 time units from their nominal “zero” skew position. The completely integrated PLL allows cancellation of external load and transmission line delay effects. When this “zero delay” capability of the PSCB is combined with the selectable output skew functions, you can create output-to-output delays of up to ±12 time units. Divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. When combined with the internal PLL, these divide functions enable distribution of a low frequency clock that are multiplied by two or four at the clock destination. This facility minimizes clock distribution difficulty, allowing maximum system clock speed and flexibility. Logic Block Diagram TEST FB REF VCO AND TIME UNIT GENERATOR FS SELECT INPUTS (THREE LEVEL) SKEW SELECT MATRIX 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 FILTER PHASE FREQ DET Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 38-07138 Rev. *B Revised June 22, 2007 [+] Feedback Document Number: 38-07138 Rev. *B Page 2 of 19 [+] Feedback 3Q1 3Q0 V CCN FB V CCN 2Q1 2Q0 3F0 FS V CCQ REF GND TEST 2F1 Pin Definitions Signal Name IO Description REF I Reference frequency input. This input supplies the frequency and timing against which all functional variations are measured. FB I PLL feedback input (typically connected to one of the eight outputs). FS I Three level frequency range select. See Table 1. 1F0, 1F1 I Three level function select inputs for output pair 1 (1Q0, 1Q1). See Table 2. 2F0, 2F1 I Three level function select inputs for output pair 2 (2Q0, 2Q1). See Table 2. 3F0, 3F1 I Three level function select inputs for output pair 3 (3Q0, 3Q1). See Table 2. 4F0, 4F1 I Three level function select inputs for output pair 4 (4Q0, 4Q1). See Table 2. TEST I Three level select. See “Test Mode” on page 4 under the “Block Diagram Description” on page 3. 1Q0, 1Q1 O Output pair 1. See Table 2. 2Q0, 2Q1 O Output pair 2. See Table 2. 3Q0, 3Q1 O Output pair 3. See Table 2. 4Q0, 4Q1 O Output pair 4. See Table 2. VCCN PWR Power supply for output drivers. VCCQ PWR Power supply for internal circuitry. GND PWR Ground. 3F1 4F0 4F1 VCCQ VCCN 4Q1 4Q0 GND GND 5 4 3 2 1 32 31 30 29 6 28 7 27 8 26 CY7B991 9 25 CY7B992 10 24 11 23 12 22 13 21 1415 1617181920 Pin Configuration PLCC/LCC 2F0 GND 1F1 1F0 VCCN 1Q0 1Q1 GND GND CY7B991 CY7B992 CY7B991 CY7B992 Block Diagram Description Phase Frequency Detector and Filter The Phase Frequency Detector and Filter blocks accept inputs from the reference frequency (REF) input and the feedback (FB) input and generate correction information to control the frequency of the Voltage Controlled Oscillator (VCO). These blocks, along with the VCO, form a Phase Locked Loop (PLL) that tracks the incoming REF signal. VCO and Time Unit Generator The VCO accepts analog control inputs from the PLL filter block. It generates a frequency used by the time unit generator to create discrete time units that are selected in the skew select matrix. The operational range of the VCO is determined by the FS control pin. The time unit (tU) is determined by the operating frequency of the device and the level of the FS pin as shown in Table 1. Table 1. Frequency Range Select and tU Calculation[1] FS[2, 3] fNOM (MHz) where N = tU 1 fNOM . N --------- ---- ----- - -- = ApproximateFrequency (MHz) AtWhich tU = 1.0 nsMin Max LOW 15 30 44 22.7 MID 25 50 26 38.5 HIGH 40 80 16 62.5 Skew Select Matrix The skew select matrix contains four independent sections. Each section has two low skew, high fanout drivers (xQ0, xQ1), and two corresponding three level function select (xF0, xF1) inputs. Table 2 shows the nine possible output functions for each section as determined by the function select inputs. All times are measured with respect to the REF input assuming th...
Este manual também é adequado para os modelos :Gravadores Tempo - CY7B992 (374.49 kb)