Assessments - 2, GPA: 3.5
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10K ohm series resistor to MAB#12. 200 ohm pull-up to 3.3V at CK100. DP: connect between CPUs (Logic may be provided to detect a frequency match). A[35:32]#, A[31:3] Leave as NC, connect A[31:3]# to 82443GX. A20M# 150 ohm - 330 ohm pull-up to 2.5V. ADS# UP: Connect to 82443GX; DP: Connect CPUs and 82443GX AERR# Leave as NC. AP[1:0]# Leave as NC. BCLK Connect to CK100. 22 ohm series resistor. BERR# Leave as NC. BINIT# Leave as NC. BNR# UP: Connect to 82443GX; DP: Connect CPUs and 82443GX BP[3:2]# Leave as NC. BPM[1:0] Leave as NC. BPRI# UP: Connect to 82443GX; DP: Connect CPUs and 82443GX. BREQ[1:0]# UP: Connect BREQ0# to 82443GX. Leave BREQ1# as NC. DP: Connect BREQ0# of each CPU to BREQ1# of the other. Connect one of these to 82443GX. D[63:0]# UP: Connect to 82443GX; DP: Connect CPUs and 82443GX. Intel® 440GX AGPset Design Guide Design Checklist Table 3-1. Slot Connectivity (Sheet 2 of 3) Processor Pin Pin Connection DBSY# UP: Connect to 82443GX; DP: Connect CPUs and 82443GX. DEFER# UP: Connect to 82443GX; DP: Connect CPUs and 82443GX. DEP[7:0] No connect. DRDY# UP: Connect to 82443GX; DP: Connect CPUs and 82443GX. EMI Connect to GND. FERR# UP: Connect to PIIX4E, 220 ohm pull-up to 2.5V. DP: Connect CPUs and PIIX4E, 220 ohm pull-up to 2.5V. FLUSH# UP: 510 ohm pull-up to 2.5V. DP: Connect CPUs and 510 ohm pull-up. FRCERR# Leave as NC. HIT# Connect between CPUs and 82443GX. HITM# Connect between CPUs and 82443GX. IERR# Leave as NC. IGNNE# UP: 330 ohm pull-up to 2.5V. Connected to bus frequency strapping circuit. DP: Connect CPUs, bus frequency strapping unit, and 330 ohm pull-up to 2.5V. INIT# UP: Connect to PIIX4E, 330 ohm pull-up to 2.5V. DP: Connect CPUs and PIIX4E, 330 ohm pull-up to 2.5V. LINT[1:0] UP: 150 ohm - 330 ohm pull-up to 2.5V. DP: Connect CPUs and 150 ohm - 330 ohm pull- up to 2.5V. LOCK# UP: Connect to 82443GX; DP: Connect CPUs and 82443GX. PICCLK Connect to CK100. 22 ohm series resistor. PICD[1:0] UP: 150 ohm pull-up to 2.5V. DP: Connect CPUs and IOAPIC and 150 ohm pull-up to 2.5V. PRDY# 240 ohm series resistor to ITP. PREQ# Connected to ITP. 330 ohm pull-up to 2.5V. PWRGOOD UP: Requires 330 ohm pull-up to 2.5V. DP: Connect between CPUs. REQ[4:0]# UP: Connect to 82443GX; DP: Connect CPUs and 82443GX. RESET# UP: Connect to 82443GX, 240 ohm series resistor to ITP. DP: Connect CPUs and ITP with 240 ohm series resistor. RP# Leave as NC. RS[2:0]# UP: Connect to 82443GX; DP: Connect CPUs and 82443GX. RSP# Leave as NC. SLOTOCC# UP: Tie to GND. DP: Part of PWRGD logic, 8.2K ohm pull-up to 3.3V. SLP# UP: 150 ohm - 330 ohm pull-up to 2.5V. Connect to PIIX4E. DP: Connect CPUs and PIIX4E with 150 ohm - 330 ohm pull-up to 2.5V. SMI# UP: Connect to PIIX4E, 430 ohm pull-up to 2.5V. DP: Connect CPUs and run to jumper on APC_SMI# and PX4_SMI# (on IOAPIC). 430 ohm pull-up to 2.5V. STPCLK# UP: Connect to PIIX4E, 430 ohm pull-up to 2.5V. DP: Connect CPUs and PIIX4E, 430 ohm pull-up. TCK UP: 1K ohm pull-up to 2.5V. 47 ohm series resistor to ITP. DP: Separate series resistors then hooked together to ITP. 1K ohm pull-up to 2.5V. Intel® 440GX AGPset Design Guide Design Checklist Table 3-1. Slot Connectivity (Sheet 3 of 3) Processor Pin Pin Connection TDO UP: Connected to ITP. 150 ohm pull-up to 2.5V. DP: Connected to jumpers between ITP and CPU signals. See DP schematics for details. TDI UP: Connected to ITP. 150 ohm - 330 ohm pull-up to 2.5V. DP: Connected to jumpers between ITP and CPU signals. See DP schematics for details. TESTHI UP: 4.7K ohm pull-up to 2.5V. DP: Connect CPUs and 4.7K ohm pull-up to 2.5V. THERMTRIP# UP: NC if not used. 220 ohm pull-up to 2.5V if used. DP: Connect CPUs and 220 ohm pull-up to 2.5V. TMS UP: 1K ohm pull-up to 2.5V. 47 ohm series resistor to ITP. DP: Separate 47 ohm series resistors then hooked together to ITP. 1K ohm pull-up to 2.5V. TRDY# UP: Connect to 82443GX. DP: Connect CPUs and 82443GX. TRST# UP: Connect to ITP. 680 ohm pull-down. DP: Connect CPUs and 680 ohm pull-down. VID[4:0] 8.2K ohm pull-up to 5V is the default for VRM use. Optional override could be used. Also connect to optional LM79. Table 3-2. GND & Power Pin Definition GND VccCORE Vtt (1.5V) VCC3 (3.3V) Reserved (NC) Vcc (5V) A2 A62 B13 B89 A1 B113 A16 B109 A6 A66 B17 B93 A3 B117 A47 A10 A70 B25 B97 B5 B121 A88 A14 A74 B29 B105 B9 A113 A18 A78 B33 A116 A22 A82 B37 B12 A26 A86 B45 B20 A30 A90 B49 B112 A34 A94 B53 A38 A98 B57 A42 A102 B65 A46 A106 B69 A50 A110 B73 A54 A114 B77 A58 A118 B85 Intel® 440GX AGPset Design Guide Design Checklist 3.3.2 Intel® Pentium® II Processor Clocks • Include a circuit for the system bus clock to core frequency ratio to the processor. The ratio should be configurable as opposed to hard wired. The bus frequency select straps will be latched on the rising edge of CRESET#. • CRESET# is used as the selection signal for muxing A20M#, IGNNE#, INTR, and NMI with the processor bus/core frequency selection jumpers. A ‘244 buffer maybe used as a mux. The outputs of the ‘244 device are fed to open ...
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