Assessments - 2, GPA: 4 ( )

Fabricante : Cypress Arquivo Tamanho: 389.61 kb Arquivo Nome : 22e7bf67-cb03-4b32-bed0-7813f15c1ea8.pdf Língua de Ensino:

SRAM uses rising edges only ¦ Echo clocks (CQ and CQ) simplify data capture in high speed systems ¦ Data valid pin (QVLD) to indicate valid data on the output ¦ Synchronous internally self-timed writes [1] ¦ Core VDD = 1.8V ± 0.1V; IO VDDQ = 1.4V to VDD ¦ HSTL inputs and variable drive HSTL output buffers ¦ Available in 165-ball FBGA package (15 x 17 x 1.4 mm) ¦ Offered in both in Pb-free and non Pb-free packages ¦ JTAG 1149.1 compatible test access port ¦ Delay Lock Loop (DLL) for accurate data placement Configurations With Read Cycle Latency of 2.0 cycles: CY7C1246V18 – 4M x 8 CY7C1257V18 – 4M x 9 CY7C1248V18 – 2M x 18 CY7C1250V18 – 1M x 36 Selection Guide Functional Description The CY7C1246V18, CY7C1257V18, CY7C1248V18, and CY7C1250V18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II+ architecture. The DDR-II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of both K and K. Each address location is associated with two 8-bit words (CY7C1246V18), 9-bit words (CY7C1257V18), 18-bit words (CY7C1248V18), or 36-bit words (CY7C1250V18) that burst sequentially into or out of the device. Asynchronous inputs include output impedance matching input (ZQ). Synchronous data outputs (Q, which share the same physical pins with the data inputs, D) are tightly matched to the two output echo clocks CQ/CQ, eliminating the need to capture data separately from individual DDR SRAMs in the system design. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Description 375 MHz 333 MHz 300 MHz Unit Maximum Operating Frequency 375 333 300 MHz Maximum Operating Current 1210 1080 1000 mA Note 1. The QDR consortium specification for VDDQ is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting VDDQ = 1.4V to VDD. Cypress Semiconductor Corporation Document Number: 001-06348 Rev. *D• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 11, 2008 [+] Feedback [+] Feedback[+] Feedback CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Logic Block Diagram (CY7C1246V18) A(20:0) CLK Gen. K K Control Logic Address Register Read Add. Decode Read Data Reg. R/W Output Logic Reg. Reg. Reg. 8 8 16 8 NWS[1:0] VREF Write Add. Decode 8 8 LD Control 21 2M x 8 Array2M x 8 Array Write Reg Write Reg R/W DOFF 8 CQ CQ DQ[7:0] QVLD Logic Block Diagram (CY7C1257V18) A(20:0) CLK Gen. K K Control Logic Address Register Read Add. Decode Read Data Reg. R/W Output Logic Reg. Reg. Reg. 9 9 18 9 BWS[0] VREF Write Add. Decode 9 9 LD Control 21 2M x 9 Array2M x 9 Array Write Reg Write Reg R/W DOFF 9 CQ CQ DQ[8:0] QVLD Document Number: 001-06348 Rev. *D Page 2 of 27 [+] Feedback [+] Feedback[+] Feedback CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Logic Block Diagram (CY7C1248V18) A(19:0) CLK Gen. K K Control Logic Address Register Read Add. Decode Read Data Reg. R/W Output Logic Reg. Reg. Reg. 18 18 36 18 BWS[1:0] VREF Write Add. Decode 18 18 LD Control 20 1M x 18 Array1M x 18 Array Write Reg Write Reg R/W DOFF 18 CQ CQ DQ[17:0] QVLD Logic Block Diagram (CY7C1250V18) A(18:0) CLK Gen. K K Control Logic Address Register Read Add. Decode Read Data Reg. R/W Output Logic Reg. Reg. Reg. 36 36 72 36 BWS[3:0] VREF Write Add. Decode 36 36 LD Control 19 512K x 36 Array512K x 36 Array Write Reg Write Reg R/W DOFF 36 CQ CQ DQ[35:0] QVLD Document Number: 001-06348 Rev. *D Page 3 of 27 [+] Feedback [+] Feedback[+] Feedback CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Pin Configurations 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1246V18 (4M x 8) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/72M A R/W NWS1 K NC/144M LD A A CQ B NC NC NC A NC/288M K NWS0 A NC NC DQ3 C NC NC NC VSS A A A VSS NC NC NC D NC NC NC VSS VSS VSS VSS VSS NC NC NC E NC NC DQ4 VDDQ VSS VSS VSS VDDQ NC NC DQ2 F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC G NC NC DQ5 VDDQ VDD VSS VDD VDDQ NC NC NC H DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ VDD VSS VDD VDDQ NC DQ1 NC K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC L NC DQ6 NC VDDQ VSS VSS VSS VDDQ NC NC DQ0 M NC NC NC VSS VSS VSS VSS VSS NC NC NC N NC NC NC VSS A A A VSS NC NC NC P NC NC DQ7 A A QVLD A A NC NC NC R TDO TCK A A A NC A A A TMS TDI CY7C1257V18 (4M x 9) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/72M A R/W NC K NC/144M LD A A CQ B NC NC NC A NC/288M K BWS0 A NC NC DQ3 C NC NC NC VSS A A A VSS NC NC NC D NC NC NC VSS VSS VSS VSS VSS NC NC NC E NC NC DQ4 VDDQ VSS VSS VSS VDDQ NC NC DQ2 F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC G NC NC DQ5 VDDQ VDD VSS VDD VDDQ NC NC NC H DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ VDD VSS VDD VDDQ NC DQ1 NC K N...

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