Assessments - 2, GPA: 4
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ICs IC7B00~IC7B03 are level shift ICs, changing the 3.3V data and clock lines from IC7A00 to 5V lines. In previous sets the TV Control circuitry used two E2PROM Memory ICs, one on the PCB-SIGNAL and one on the PCB-TERMINAL. Due to the changes in design only one E2PROM is required, and for factory alignment purposes it is located on PCB-TERMINAL. In the V23 the DTV Tuner and Modulator are separate from the DM Module. The DTV Tuner is controlled by the TDAT and TCLK lines from the DM Module. The DM Module also controls the MLink (DVI) circuitry, through the DVI-RXD and DVI-TXD lines. Figure 4-4 also shows that the DM Module receives and processes the signals from the Card Reader. .PC Parallel Inputs The parallel inputs to the .PC are status inputs or signals inputs required for control purposes. AC-OFF Input Informs the .PC if AC Power is lost. The monitoring circuit is shown in Figure 4-5. Samples of the input AC are applied to the base of Q9A10. D9A16 removes the negative half of the sine waves. The remaining positive half cycles keep Q9A10 conducting. With Q9A10 conducting PC9A10 conducts, turning Q7A20 On. The conduction of Q7A20 holds the AC-OFF input to IC7A00 Low. If AC power is lost, Q9A10, PC9A10 and Q7A20 all quit conducting, allowing pin 20 of IC7A00 to go High. This informs the Control circuitry power has been lost. The .PC responds by rapidly storing all user programming and service adjustments to memory. It also outputs a High on the Power Good line, informing the DM of the power loss. 4-6 SHORT Detect The short Detect circuitry is shown in Figure 4-6 and is the same as in the V19 and V21 chassis. If a short occurs in the + or – 24V supplies, pin 46 on IC7A00 goes Low indicating a short and the TV shuts Off. With -24V shorted, the 12VS supply turns Q9A53 On, pulling the SHORT line Low. If +24V is shorted D9A54 is forward biased and the short line goes Low. X-RAY Protect Refer to Figure 4-7, the X-Ray input is at pin 47 of IC7A00, and is normally High. The X-Ray Protect circuit monitors: • Excessive HV • Excess CRT Beam Current • Excess HV circuit Current If any of the preceeding occurs, the X-Ray line goes Low, and the TV shuts Off. The monitoring circuits for X-ray Protect are described in the detail in the Deflection and HV Section. Other parallel inputs to the .PC, are listed in Table 4-1. IC7A00 Additional Inputs Pin # Name Source 6 SD-SUB Sub Tuner Sync Detector 7 SD-MAIN Main Tuner Sync Detector 62 H-SYNC-IN ASIC Horizontal Sync 64 V-SYNC-IN ASIC Vertical Sync 92 AFT1 Main Tuner AFT voltage. 93 AFT2 Sub Tuner AFT voltage 94 VBLK Deflection Loss Detect circuit 97 CV-IN-SUB Sub Video (CCD, V-chip,etc) 100 CV-IN-MAIN Main Video (CCD, V-chip,etc) Table 4-1: .PC Inputs Additional IC7A00 Outputs Pin # Name Purpose 42 BLNK-CRT Blanks CRTs during Input &Channel changes. 49 PON-2 Power ON: (Defl, Conv, HV, etc. circuitry) 50 PON-1 Power ON: Signal Processing circuitry) 51 BWC Band Width Control for Doubler Output 52 F Sets the Free Run Horizontal Frequency 56 F31K Decreases H-Defl DC supply for 31.5 kHz. 57 DEFL-MUTE Decreases H-Defl DC supply during freq. change. 71 BLK-EN Enables OSD Insertion 76 MUTE SUB Mutes Sub Picture Audio Output 80 MUTE SPKR Mutes the TV's Speakers 82 POWERGOOD Informs the DM that the DC Power is ok 86 MUTE MON Mutes Monitor Out Audio 87 SUB POWER Activates/Deactivates the Economy Mode Table 4-2: .PC Outputs Parallel Outputs Most of the parallel outputs are listed in Table 4-2. Most of them have been used before and need no explanation. However, the function of two items should be described. BWC (Band Width Control) This line is directed to the Doubler circuitry, and automatically becomes active when the signal source is NTSC. The Doubler circuit is designed to produce the best possible picture for an HDTV signal. Due to this design, artifacts may appear in the picture when the signal source is NTSC. With an NTSC source, the BWC line automatically goes High. The High reduces some of the high frequency output from the Doubler, removing the unwanted artifacts. BLK-EN Figure 4-8 illustrates the BLK-EN circuitry. The BLK-EN selects the path for the OSD insertion timing signal (DM-BLK). The OSD signals and the DM-BLK timing signal are generated in the DM Module. If the source signal is not from the DTV Tuner or a 1394 input, the OSD signal is inserted in the main signal in the VCJ IC2V01. The Timing Signal (DM-BLK) is applied to the inputs of IC2V02 and ICSVO3. IC2V02 directs the signal to the VCJ, and IC2V03 directs the signal to the Doubler circuit. The path of the DM-BLK signal is determined by BLK-EN from the TV .PC. BLK-EN is applied directly to the OE (Output Enable) input of IC2V03, and is inverted by Q2X04 and applied to the OE input of IC2V02. IC2V02 and IC2V03 are enabled when their OE input GOES Low. When EN-BLK is High, IC2V02 is enabled and the DM-BLK is directed to the VCJ. When EN-BLK is Low, DM-BLK is directed to the Doubler. DM-BLK is needed in Doubler, even th...
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