Assessments - 3, GPA: 4.3 ( )

Fabricante : Mitsubishi Electronics Arquivo Tamanho: 3.06 mb Arquivo Nome : Língua de Ensino:

The Deflection Loss Detection circuit is similar to previous models, as shown in Figure 6-7. Q4B01 monitors vertical deflection, and Q5A38 monitors horizontal deflection. The conduction of both transistors holds their respective collector voltage below the forward bias point of the diode in their collector circuit's (D4B04 or D5A12). If either Q4B01 or Q5A38 stop conducting, indicating a loss of deflection, the increase in that transistor’s collector voltage drives the V-Blank line High. The V-Blank line goes to the CRT Protect circuitry and immediately removing all drive to the CRTs. 6-8 HV & HV Regulation Figure 6-8 illustrates the HV and HV Regulation circuitry. Drive from the Horizontal Deflection Output circuitry is applied the HD-IN input of IC5A00. IC5A00 amplifies the signal which is output at pin 1, and through Q5A07 and Q5A09, is applied to the gate of Q5A51. The output of Q5A51 is the drive signal for the Flyback transformer, T5A51. In the Flyback, the signals are stepped up and rectified to generate the HV and Focus voltages for the three CRTs. The amount of HV generated depends of the conduction time of Q5A51, the longer the conduction time the more energy supplied to the Flyback, and HV increases. HV is regulated by controlling the duty cycle of the drive signal to Q5A31. A sample of the HV, HV-DC-FB, is derived from an internal resistive divider in the Flyback and is output at pin 13. The HV sample is applied to the noninverting input of an OP-Amp in IC5A01. The HV ADJ voltage in applied to the inverting input of a second OP-Amp in IC5A01. The outputs of both OP-Amps are combined and directed to pin 4 of IC5A00. 6-9 DO NOT measure the HV-DC-FB voltage at pin 13 of the T5A51. The meter may load down the internal resistive divider, resulting in excessive HV. X-Ray Protect X-Ray Protect circuitry is the basically the same as in previous models, as shown in Figure 5. The XRay Protect circuit in the V20 monitors three items: 1) Q5A51 (HV Output) current, by monitoring Q5A51 source voltage. 2) Excessive HV, by monitoring the rectified voltage from D5A57. 3) Excessive CRT Beam current, by monitoring the voltage at pin 8 for T5A51. Each of the monitored sources is applied to an input of an OP-Amp in IC5A02. The second input of each OP-Amp is connected to a specific reference. The outputs of all three Op-Amps are tied together at the X-Ray line. The X-Ray line is normally High. If any of the monitored sources exceeds its’ specific reference the XRay line is pulled Low, shutting Off the TV. The connection from the source of Q5A51 to pin 5 of IC5A00 provides further protection. If the source voltage becomes excessive (excess current), IC5A00 immediately removes all drive to Q5A51. 6-10 Q5A20 and its associated circuitry comprise an Arc Protect circuit. If a CRT Arcs this circuitry immediately removes HV Drive. If X-Ray Protect shuts the TV Off, pressing the Power button will turn the TV back On (it may shut Off again if the problem still exists). If Arc Protect is activated, the TV must be switched Off before it can be switched back On. Chapter 7 Convergence Circuitry Figure 7-1: Convergence Circuitry - Overall Block Diagram The Overall Block Diagram in Figure 7-1 shows the the V23 Convergence Circuitry.. A Waveform Generator generates the convergence correction signals timed from horizontal and vertical sync pulses. The correction signals from the Waveform Generator are in a serial digital format. The following Digital/Analog Converter changes the digital signals to analog signals. The analog signals from the D/A Converter are directed LPF (Low Pass Filter) and Summing Amplifiers. Any remaining high frequency digital signals are removed and the analog correction signals are amplified. Green correction signals are added to the red and blue signals in the Amplifiers, hence the name Summing Amplifiers. The correction signals are amplified by Output Amplifiers and are directed to the sub coils in their respective Deflection Yokes. This is the same basic circuitry used in the last few chassis types. There are only two major differences in V23 Convergence circuitry compared to that in the V21. 1) In the V23, the Waveform Generator is on the PCB-SIGNAL, not on a separate plug-in PCB. 2) Two Convergence Output ICs are used in the V23, only one was used in the V19. 7-1 7-2 Waveform Generator & D/A Converter Figure 7-2 illustrates the Convergence Waveform Generator and Digital/Analog Converter circuitry. Horizontal Sync from the doubler circuitry is applied to pin 34 of IC8D00. Vertical Sync is applied to pin 27. From these two signals, IC8D00 generates six Convergence Correction signals, consisting of horizontal and vertical correction signals for each CRT. Correction signals from IC8D00 are converted to analog signals in IC8E03 and are then directed to LPF and Summing Amplifiers. Convergence Control signals are also shown in Figure 7-2. These include: • C-SCL … Serial Clock • C-SDA … I2C Data line • C-MUTE … d...

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