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Due to the concerns over the availability and increasing cost of DDR, AMD has developed a method for operating DDR2 memory with the processor’s memory controller. This application note details the software changes necessary to enable this technology. Note: The solution described in this document does not conform to the JEDEC DDR2 Specification. This solution may not work with all DDR2 memory. Note: This is revision B of this document. The change from revision A (also dated March 2009) is “AMD Confidential” was removed. 2.0 Description Initializing DDR2 SDRAM requires writing to additional mode registers. In addition to the Mode Register (MR) and Extended Mode Register (EMR), DDR2 defines two new Extended Mode Registers, EMR(2) and EMR(3). The EMR is renamed as EMR(1). Furthermore, the MR and EMR definitions are not an exact match between DDR and DDR2. Table 2-1 shows a comparison of the typical initialization steps for DDR vs. DDR2. Addressing MR vs. EMR(1), EMR(2) or EMR(3) is determined by the states of BA[2:0] while the LOAD MODE command is presented on the control signals. The data written to the registers is the pattern presented on A[15:0] when the command is initiated. (Note, however, that A[15:13]=0, and BA[2]=0 in all cases.) Software on the LX processor issues LOAD MODE commands by writing the MC_CF07_DATA register. During the operation, the memory controller (MC) uses various bits and fields in the MC_CF07_DATA and MC_CF8F_DATA registers. With the available settings, the LX processor is not capable of generating the necessary signal patterns for all the required LOAD MODE commands. Table 2-1. Initialization Steps DDR DDR2 Wait a minimum of 200.s after clocks and power are stable, then assert CKE. Wait a minimum of 200.s after clocks and power are stable, then assert CKE. Wait a minimum of 400ns, then issue a PRECHARGE ALL command. Wait a minimum of 400ns, then issue a PRECHARGE ALL command. Issue a LOAD MODE command to EMR(2) Issue a LOAD MODE command to EMR(3). Issue a LOAD MODE command to EMR to enable the DLL. Issue a LOAD MODE command to EMR(1) to enable the DLL. Issue LOAD MODE command to MR with DLL reset. Issue LOAD MODE command to MR with DLL reset. Wait at least 200 clock cycles. Issue a PRECHARGE ALL command. Wait at least 200 clock cycles. Issue a PRECHARGE ALL command. Issue two REFRESH commands. Issue two REFRESH commands. Issue LOAD MODE to MR without DLL reset. Issue LOAD MODE to MR without DLL reset. Issue LOAD MODE to EMR(1) with OCD default. Issue LOAD MODE to EMR(1) with OCD exit. SDRAM initialization is complete. SDRAM initialization is complete. 46959A - March 2009 Application Note 46959A - March 2009 3.0 Solution The method for initializing DDR2 memory on the processor is to insert a CPLD and quick switches in the address and BA signals. Figure 3-1 shows a block diagram of this design. During initialization, the Enable signal opens (default) the switches. BIOS tells the CPLD what pattern to assert on the BA[n] and A[n] signals. Upon completion, BIOS tells the CPLD to close the switches, giving control over BA[n] and A[n] to the processor. Additional physical and electrical details of the design are beyond the scope of this document. 3.1 Hardware This section explains the details of the initialization. First it’s important to delineate two unique versions of this hardware technology. 3.1.1 On-DIMM Design This hardware form-factor has a DDR pin assignment (only SO-DIMM as of this writing), but contains DDR2 SDRAM modules, and the CPLD. This type of design will be attractive for customers wanting to upgrade existing systems. The only board change required is a lower memory voltage. Because the CPLD is contained on the DIMM assembly, the only bus available for communication is I2C. The CPLD’s I2C address is A0/A1 (i.e., the same as DIMM0). The CPLD also contains the SPD information. Also note that the CPLD uses CKE as its RESET# signal. As a result, the list of BIOS changes may require moving the assertion of CKE (e.g., if the SPD is accessed prior to CKE). 3.1.2 On-board Design This type of system will have the CPLD soldered onto the motherboard, and will be able to use certain off-the-shelf (OTS) DDR2 DIMMs. In this case, the CPLD does not contain SPD information. Because the communication is not limited to I2C, using I/O to send data to the CPLD simplifies the CPLD design and speeds up initialization. The I/O addresses selected for the AMD Geode™ LX Processor Refresh Reference Design Kit (RDK) board are AC10h and AC11h. This requires a modification to the Virtual PCI portion of the BIOS to identify the I/O range to an operating system. As of this writing, the CPLD claims a range of 8 bytes (i.e., AC10h-AC17h). AMD Geode™ LX Processor / CS5536 DDR2 SDRAM A[13] A[15:14], BA[2] Quick Switches A[12:0], BA[1:0] CPLD A[12:0], BA[1:0] Enable I2C Figure 3-1. AMD Geode™ LX Processor DDR2 Block Diagram AMD Geode™ LX Processor DDR2 BIOS Porting Guide Application Note 46959A - March 2009...